sames
FEATURES
UNIVERSAL PABX TONE GENERATOR
s
Generates PBX supervisory tones in
PCM format
s
Integrated time slot allocation circuitry
s
No noticeable level changes in tones
s
Frame synch. signal source (internal/
external) selectable
s
Eight tone programs
s
Eight independent PCM tone streams
within each program
4092
PDS039-SA9401-001 REV. C 07-05-96
SA9401
s
Each of these tone streams selectable
from 16 tone blocks
s
Seperate Intrude Tone for each pro-
gram
s
Choice of clock frequencies
s
Watchdog facility
s
Low power CMOS technology
PROGRAMMABLE FEATURES
s
Tone samples
s
Tone Cadence timing
s
Tone to time-slot mapping
s
Size of tone blocks
s
Intrude tone frequency
s
Intrude tone cadence
s
"silence sample" value
DESCRIPTION
The SA9401 operates in conjunction with a standard EPROM to generate the system
tone plans for the PABX systems of most major countries.
The high level of programmability allows the SA9401 to satisfy a wide variety of tone
plans. Furthermore by providing three inputs to select between one of eight tone
programs during initialisation, the device effectively facilitates the design of a universally
programmable "PABX Processor Card". Because the tone program inputs are latched
at the start of each PCM frame the SA9401 minimises the possibility of glitches.
The SA9401 can also generate the PCM Frame synchronising reference signal if
required.
sames
SA9401
2
Package : PLCC - 44
D2
SA9401
INTRFRQ
CLKIN
A6
A5
PCMFSC
DR-00603
3
4
5
6
PS0
2MCLK
CLKDIV2
8KFS
8
7
9
10
A4
GND
A3
A2
A1
A0
CLK_SEL
40
41
42
43
44
1
2
D1
D0
A7
MRST
36
37
39
38
PS2
PCM_OUT
15
INTRCAD
PS1
V CC
11
14
13
12
WD_EN
WD_RST
16
17
21
18
19
20
WD_INT
A13
A12
D5
31
D4
D3
V
CC
35
34
33
32
26
24
22
23
25
27
28
D7
D6
30
29
TEST
A10
GND
A11
A9
A8
FS1
PIN DESCRIPTION
1, 23
I
GND
Supply Ground
12, 34
I
VCC
+5V Power Supply
27
I
FS1
Frame Synchronisation (active low)
6
I
CLKIN
Master clock input (either 8192kHz or 2048 Khz
dependent on logic level of "CLK _SEL")
8
O
2MCLK
2048 kHz clock derived internally from CLKIN
10
O
8KFS
8 kHz Frame Synchronisation output.
5
O
PCMFSC
8 kHz Auxilliary Frame Synchronisation Output
11
O
INTRFRQ
Square Wave Intrude Tone
13
O
INTRCAD
Intrude Tone Cadence Signal
15
O
PCM_OUT
Tri-state PCM Highway tone output
41, 42, 43, 44,
O
A0..A13
EPROM Address Lines
2, 3, 4, 39, 26,
25, 22, 24,
21, 20
Pin No
I/0
Designation
Description
sames
SA9401
3
37, 36, 35, 33,
I
D0..D7
EPROM Data Lines
32, 31, 30, 29
9, 14, 19
I
PS0, PS1,
Program Select Inputs for Selecting
PS2
between 1 of 8 tone plans
7
O
CLKDIV2
CLKIN divided by 2 output (i.e. 4096 kHz or 1024
kHz depending on CLK_SEL input)
40
I
CLK_SEL
Selects between CKLIN of 8192 or 2048 kHz and
Synchronisation source.
0 = 8192kHz/Internal
1 = 2048kHz/External
28
I
TEST
Used for IC testing purpose. Tied Low during
normal operation.
38
I
MRST
Asynchronous Reset Pin. Resets all Internal Flip
Flops (active low)
16
I
WD_RST
Watchdog reset input (Rising-edge triggered) Tied
high if unused
17
I
WD_EN
Watchdog enable input (active low) Tied high if
unused
18
O
WD_INT
Watchdog output (active low, tri-state)
PIN DESCRIPTION (Continued)
Pin No
I/0
Designation
Description
BLOCK DIAGRAM
CLOCK
GENERATOR
P C M _ O U
A[13 : 0]
I N T R C A D
8 K F S
I N T R F R Q
W D _ I N T
P C M F S C
2 M C L K
C L K D I V 2
SA9401
D R - 0 1 0 8 5
T E S T
P S [ 2 : 0 ]
/ F S 1
D [ 7 : 0 ]
W D E N B
W D _ R S T
C L K I N
/ M R S T
C L K _ S E L
W A T C H D O G
TIMER
CADENCE
TIMER
P C M
INTERFACE
E P R O M
INTERFACE
INTRUDE
TONE
GENERATOR
sames
SA9401
4
FUNCTIONAL DESCRIPTION
The design of the SA9401 has been based on the assumption that any supervisory tone
used in a PABX (e.g. Dial tone or Busy Tone etc) can be described by a small set of
simple parameters and that the tones will be injected into a standard PCM 30 (2048kHz)
backplane in either A-law or -law format.
In the SA9401 a tone is created by repeating a fundamental waveform (or one of two
waveforms) which would typically be one cycle of a sinewave or alternatively may be
several cycles of a higher frequency signal (say 400 to 1000Hz) modulated by a lower
frequency signal. This Tone may then be interrupted ("Cadenced") so that the tone is
effectively switched on and off.
The waveform shape, number of samples per cycle and the cadence can all be set by
the system designer in accordance with the related National Standards.
Once a set of tones have been described they may then be injected into the PCM
backplane. The time slot associated with each tone can be set by the system designer.
The SA9401 accommodates up to 9 different Tones to form a Tone Plan making ample
allowance for Ring, Dial, Busy, Intrude and other Tones. The set of data describing one
Tone Plan (waveforms, cadence timings, timeslots etc) is referred to as a Program and
is stored in an external EPROM which is addressed directly by the SA9401.
Up to eight Tone Plans may be stored and selected at will to accommodate products for
multi-national markets.
ARCHITECTURE
The architecture of the SA9401 consists of 6 functional blocks each of which is de-
scribed in detail in the following sections. Refer also to the block diagram.
Clock Generator
The clock generator circuit derives all the timing for the ic from either a 2048kHz or a
8192kHz clock. The desired Clock is selected by the state of the CLK_SEL pin (1 for
2048kHz and 0 for 8192kHz).
The CLK_SEL pin also determines the function of the Frame Sync pin. If CLK_SEL is
low then Internal synchronisation is assumed and FS1 should be tied high. If CLK_SEL
is high then an external Frame Synchronisation source must be connected to /FS1.
The Clock Generator comprises 5 functional blocks.
A divide-by-4 counter is enabled only if a 8192kHz clock is selected so that all internal
timing is based on 2048kHz. The Time Slot Counter keeps track of the Time Slots (0
to 31) in the PCM Frame while the bit position (0 to 7) in each time-slot is tracked by the
Bit Position Counter. PCM frame synchronisation signals are controlled by the Frame
Generator. Long cadence intervals are accommodated by the Five-ms-Timebase
which delivers a 200Hz signal which clocks the Cadence Timers.
sames
SA9401
5
Intrude Tone Generator
This module generates a square wave output based on the master clock of 2048kHz.
The Intrude Tone frequency is determined by the contents of the 16-bit Intrude Tone
Register (INTR_LO and INTR_HI) according to the formula:-
f
int
= 2048kHz/(2*(n+1))
where n is the content of the INTR register.
The range of values in the register (from 0 to 65535) give Intrude tones in the range
15.625Hz to 1024kHz.
Cadence Timer
In any given Tone Plan the SA9401 assumes that any or all of the 9 (8 PCM tone
streams and one squarewave Intrude Tone) tones are required to have their own inde-
pendently defined cadence. A typical cadence is illustrated in FIGURE 1 above. Each
tone is assumed to comprise up to 4 cadence periods which repeat cyclically. The
duration of each period is controlled by the Cadence Timers which in turn comprise 10-
bit Counters. These timers are clocked by the five_ms_timebase generated by the
Clock Generator so that intervals of up to 5.12 seconds can be defined with a resolution
of 5ms. (10 bits => 1023: 1023*5ms = 5115ms)
The Cadence Controller controls the loading of the 10-bit counter and the sequencing
of the Cadence Position Counter. The duration of each period of the tone is denoted by
the parameter:-
CADm_n_LO = Period m, Tone stream n low-order 8 bits and
CADm_n_HI = Period m, Tone stream n high-order 2 bits
where 0
m
3 and 0
n
8 (8 = Intrude Tone)
The Cadence Position Counter keeps track of the period being generated and during
period 0 the SA9401 generates a tone based on one Tone Block (A) while during the
period 2 (if used) the samples from another Block (B) are used. During periods 1 and 3
the silence sample is transmitted. This feature allows the sound of the tone to be
altered along with the cadence.
A continuous tone is created by loading values of 1(or any non-zero value),0,0,0 into
the registers CAD0_n to CAD3_n respectively. The zero value is interpreted by the
SA9401 as an instruction to ignore the period and to process the next one. With the
register contents shown the Cadence Controller continuously processes the first (ON)
period.
C A D O _ n
TONE_n_A
DR-01086
ON
OFF
C A D 1 _ n
ON
C A D 2 _ n
TONE_n_B
OFF
C A D 3 _ n
FIGURE 1: TONE CADENCING
PDF 
ZIP